Golfer, Undergraduate Research Assistant in power and nano semiconductor devices,
with solid skills in nanofabrication and TCAD simulation. Sometimes I am also a musican....
Hello! My name is Zonghao (Seven) Zhang, and I am a senior pursuing a dual degree at the University of Electronic Science and Technology of China (UESTC) and the University of Glasgow. I have a strong academic foundation and hands-on experience in Electronic Engineering, with a focus on semiconductor devices, nanoelectronics, and power electronics. Beyond academics, I am actively involved in leadership and creative pursuits. As a Student Representative Council (SRC) member at the University of Glasgow, I advocate for students' welfare. I also founded UESTC’s Jazz Enthusiasts Association, promoting jazz culture, and serve as the Vice President of the Piano Club, where I enjoy performing and collaborating with fellow musicians. In my free time, I stay active through sports like basketball, golf, and billiard, which inspire teamwork and resilience. My research includes interfacial dipole engineering at the University of Notre Dame and the development of p-GaN HEMTs and Split-Gate Trench Power MOSFETs using TCAD tools. I’ve presented findings at conferences and contributed to journals. Through my diverse experiences, I aim to contribute to engineering innovation and foster vibrant interdisciplinary communities. Let’s connect and explore exciting opportunities together!
As an iSURE Research Assistant under the supervision of Prof. Kai Ni at the University of Notre Dame in the summer of 2024, I gained 2 months of cleanroom nanofabrication experience at NDNano. My work focused on designing nanoscale gate stack layers with permanent dipole capping layers in MOS capacitors (MOSCAPs), utilizing structures such as Au/Al/TiN/Al₂O₃/HfO₂/SiO₂ and Au/Al/TiN/HfO₂/Al₂O₃/SiO₂ with varying EOTs (0.8 nm–1.12 nm) to investigate interfacial dipole effects for flatband voltage shifting and threshold voltage tuning. I conducted electrical characterization of the fabricated devices, including C-V measurements, leakage current analysis, and flatband voltage extraction, and verified the experimental data through numerical calculations, advancing my skills in device fabrication and characterization.
Under the guidance of Prof. Haimeng Huang, I focused on the theoretical optimization and simulation of Superjunction MOSFETs (SJ-MOSFETs). My initial research addressed temperature-dependent effects, incorporating impact ionization and deriving the Fourier electric field distribution to optimize breakdown voltage and aspect ratios. Using MATLAB for numerical calculations and MEDICI for TCAD simulations, I successfully developed a comprehensive design model for diverse thermal conditions, leading to the publication of my first research paper. Building on this, I explored the integration of high-k materials and wide bandgap semiconductors like GaN, SiC, and Ga₂O₃. By replacing the traditional p-pillar with an Hk-pillar, I optimized electric field distribution and breakdown behavior, collaborating with peers to achieve innovative design outcomes. This work further deepened my understanding of wide bandgap materials and was also published. In a subsequent project, I enhanced Split-Gate Trench MOSFETs by designing a Bottom-Trench Hk-Pillar SJ structure using advanced TCAD tools. This design reduced the peak electric field by 35% and improved FOM and BHFFOM by 25% and 40%, respectively, showcasing my ability to innovate in semiconductor device design and process optimization.
In addition to my research on power semiconductor devices, I collaborated with Prof. Aynul Islam to design a 28nm novel multi-spacer planar MOSFET with significantly improved DIBL and Subthreshold Swing performance. This project allowed me to gain hands-on experience with Silvaco Atlas and Athena, simulating advanced fabrication techniques such as Hk/MG, silicide, LDD, and gate stack deposition. Simultaneously, I conducted an in-depth study of Back-End-of-Line (BEOL) processes and advanced fabrication technologies, focusing on interconnect strategies and material integration for nanoscale devices. This combined 2-month experience provided me with a comprehensive understanding of modern nanoscale device fabrication, spanning both front-end and back-end processes, and marked my initiation into cutting-edge nanoelectronics research, bridging the gap between simulation and practical application.
GPA 17.83/22.00
GPA 3.79/4.00
High School Diploma.
